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may 2002 ? 2002 fairchild semiconductor corporation ndc7003p rev b(w) ndc7003p dual p-channel powertrench ? ? ? ? mosfet general description these dual p-channel enhancement mode power field effect transistors are produced using fairchild?s proprietary trench technology. this very high density process has been designed to minimize on-state resistance, provide rugged and reliable performance and fast switching. this product is particularly suited to low voltage applications requiring a low current high side switch. features ? ?0.34a, ?60 v. r ds(on) = 5 ? @ v gs = ?10 v r ds(on) = 7 ? @ v gs = ?4.5 v ? low gate charge ? fast switching speed ? high performance trench technology for low r ds(on) ? supersot tm -6 package: small footprint (72% smaller than standard so-8); low profile (1mm thick) d1 s2 g1 d2 s1 g2 supersot -6 tm 3 2 1 4 5 6 absolute maximum ratings t a =25 o c unless otherwise noted symbol parameter ratings units v dss drain-source voltage ?60 v v gss gate-source voltage 20 v i d drain current ? continuous (note 1a) ?0.34 a ? pulsed ?1 power dissipation for single operation (note 1a) 0.96 (note 1b) 0.9 p d (note 1c) 0.7 w t j , t stg operating and storage junction temperature range ?55 to +150 c thermal characteristics r ja thermal resistance, junction-to-ambient (note 1a) 130 c/w r jc thermal resistance, junction-to-case (note 1) 60 package marking and ordering information device marking device reel size tape width quantity .03p ndc7003p 7?? 8mm 3000 units ndc7003p
ndc7003p rev b(w) electrical characteristics t a = 25c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drain?source breakdown voltage v gs = 0 v, i d = ?250 a ?60 v ? bv dss ? t j breakdown voltage temperature coefficient i d = ?250 a, referenced to 25 c ?57 mv/ c i dss zero gate voltage drain current v ds = ?48 v, v gs = 0 v ?1 a i gss gate?body leakage, v gs = 20 v, v ds = 0 v 100 na on characteristics (note 2) v gs(th) gate threshold voltage v ds = v gs , i d = ?250 a ?1 ?1.9 ?3.5 v ? v gs(th) ? t j gate threshold voltage temperature coefficient i d = ?250 a, referenced to 25 c 3.2 mv/ c r ds(on) static drain?source on?resistance v gs = ?10 v, i d = ?0.34 a v gs = ?4.5 v, i d = ?0.25 a v gs = ?10 v,i d = ?0.34 a, t j =125 c 1.2 1.5 1.9 5 7.5 10 ? i d(on) on-state drain current v gs = ?10 v v ds = ?10 v ?1 a g fs forward transconductance v ds = ?10 v, i d = ?0.34 a 700 ms dynamic characteristics c iss input capacitance 66 pf c oss output capacitance 13 pf c rss reverse transfer capacitance v ds = ?25 v, v gs = 0 v, f = 1.0 mhz 6 pf r g gate resistance v gs = 15mv, f = 1.0 mhz 11.2 ? switching characteristics (note 2) t d(on) turn?on delay time 3.2 6.4 ns t r turn?on rise time 10 20 ns t d(off) turn?off delay time 8 16 ns t f turn?off fall time v dd = ?25 v, i d = ?1 a, v gs = ?10 v, r gen = 6 ? 1 2 ns q g total gate charge 1.6 2.2 nc q gs gate?source charge 0.3 nc q gd gate?drain charge v ds = ?25 v, i d = ?0.34 a, v gs = ?10 v 0.3 nc drain?source diode characteristics and maximum ratings i s maximum continuous drain?source diode forward current ? 0.34 a v sd drain?source diode forward voltage v gs = 0 v, i s = ?0.34 a (note 2) ?0.8 ?1.4 v notes: 1. r ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r jc is guaranteed by design while r ca is determined by the user's board design. a) 130 c/w when mounted on a 0.125 in 2 pad of 2 oz. copper. b) 140c/w when mounted on a .005 in 2 pad of 2 oz copper c) 180c/w when mounted on a minimum pad. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0% ndc7003p
ndc7003p rev b(w) typical characteristics 0 0.2 0.4 0.6 0.8 1 012345 -v ds , drain to source voltage (v) -i d , drain current (a) v gs = -10v -3.0v -4.5v -3.5v -4.0v -6.0v 0.8 1 1.2 1.4 1.6 1.8 2 2.2 00.20.40.60.81 -i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs = -3.0v -3.5v -10v -4.0v -4.5v -6.0v figure 1. on-region characteristics. figure 2. on-resistance variation with drain current and gate voltage. 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistance i d = -0.34a v gs = -10v 0 1 2 3 4 5 246810 -v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d = -0.17a t a = 125 o c t a = 25 o c figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with gate-to-source voltage. 0 0.2 0.4 0.6 0.8 1 12345 -v gs , gate to source voltage (v) -i d , drain current (a ) t a = -55 o c 25 o c 125 o c v ds = -5v 0.0001 0.001 0.01 0.1 1 10 0.2 0.4 0.6 0.8 1 1.2 -v sd , body diode forward voltage (v) -i s , reverse drain current (a) v gs = 0v t a = 125 o c 25 o c -55 o c figure 5. transfer characteristics. figure 6. body diode forward voltage variation with source current and temperature. ndc7003p
ndc7003p rev b(w) typical characteristics 0 2 4 6 8 10 00.40.81.21.62 q g , gate charge (nc) -v gs , gate-source voltage (v) i d = -0.34a v ds = -25v -30v -48v 0 20 40 60 80 100 0 102030405060 -v ds , drain to source voltage (v) capacitance (pf) c iss c oss c rss f = 1 mhz v gs = 0 v figure 7. gate charge characteristics. figure 8. capacitance characteristics. 0.01 0.1 1 10 110100 -v ds , drain-source voltage (v) -i d , drain current (a) dc 1s 100ms r ds(on) limit v gs = -10v single pulse r ja = 180 o c/w t a = 25 o c 10ms 1ms 10 s 0 2 4 6 8 10 0.001 0.01 0.1 1 10 100 t 1 , time (sec) p(pk), peak transient power (w) single pulse r ja = 180c/w t a = 25c figure 9. maximum safe operating area. figure 10. single pulse maximum power dissipation. 0.001 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) r(t), normalized effective transient thermal resistance r ja (t) = r(t) * r ja r ja = 180 o c/w t j - t a = p * r ja (t) duty cycle, d = t 1 / t 2 p (p k ) t 1 t 2 single pulse 0.01 0.02 0.05 0.1 0.2 d = 0.5 figure 11. transient thermal response curve. thermal characterization performed using the conditions described in note 1c. transient themal response will change depending on the circuit board design. ndc7003p

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